Voltage detection circuit, power-on/off reset circuit, and semiconductor device

ABSTRACT

The present invention includes a first MOS transistor whose gate and drain are connected with a first node, a second MOS transistor whose gate and drain are connected with the first node and a third node, respectively, a first resistive element which is connected between the first node and a second node, a second resistive element which is connected between the second node and a ground voltage terminal, a first NOT circuit whose input terminal is connected with the second node, whose output terminal is a fourth node, and which is connected between the third node and the ground voltage terminal, and a second NOT circuit whose input terminal is connected with the fourth node and whose output terminal is a fifth node. Consequently, the present invention can detect voltage in a stable condition with low power consumption.

FIELD OF THE INVENTION

The present invention relates to a voltage detection circuit fordetecting a power-supply voltage or the like, a power-on/off resetcircuit, and a semiconductor device.

BACKGROUND OF THE INVENTION

Recently, a technique has become popular for operating a semiconductordevice in a stable condition in a wide power-supply voltage range bychanging the internal circuit operation in accordance with thepower-supply voltage value. For this reason, a voltage detection circuitfor detecting a power-supply voltage value has become important.

A conventional voltage detection circuit will be explained hereinafterwith reference to FIGS. 23-25. FIG. 23 shows the construction of theconventional voltage detection circuit. FIG. 24 shows the relationshipbetween the power-supply voltage and the output voltage signal in theconventional voltage detection circuit. FIG. 25 shows the relationshipbetween the power-supply voltage and the current drain.

Firstly, the circuit construction will be explained. As shown in FIG.23, the Qp 61 is a P-channel type MOS transistor whose source isconnected with the power-supply voltage VDD and whose gate and train areconnected with the node N 61. The Qp 62 is a P-channel type MOStransistor whose source is connected with the node N 61 and whose gateand train are connected with the node N 62. The Qp 63 is a P-channeltype MOS transistor whose source is connected with the node N 62 andwhose gate and train are connected with the node N 63. The Qn 61 is anN-channel type MOS transistor whose source is connected with the groundvoltage VSS, whose gate is connected with the power-supply voltage VDD,and whose train is connected with the node N 63. The Qp 64 is aP-channel type MOS transistor and the Qn 62 is an N-channel type MOStransistor which compose a first NOT circuit 61. The source, gate, anddrain of the P-channel type MOS transistor Qp 64 are connected with theground voltage VDD, the node N 63, and the node N 64, respectively. Thesource, gate, and drain of the N-channel type MOS transistor Qn 62 areconnected with the ground voltage VSS, the node N 63, and the node N 64,respectively. The node N 64 is connected with the input terminal of asecond NOT circuit 62. The second NOT circuit 62 is applied with thevoltage detection signal VDT 60 from the node N 64, and generates theoutput voltage signal VOUT 60.

The operation of the voltage detection circuit will be explained asfollows. As shown in FIG. 24, the logical voltage of the output voltagesignal VOUT 60 which is obtained at the output terminal of the secondNOT circuit 62 becomes "L" when the power-supply voltage VDD is lessthan 4V and becomes "H" when the voltage VDD is about 4V or higher underpredetermined conditions.

This result is due to the following ground. The electric potential ofthe node N 63 is lower than the power-supply voltage VDD by the voltagedrop of the P-channel type MOS transistors Qp 61-Qp 63. The electricpotential becomes 2V, for example.

On the other hand, the threshold level of the first NOT circuit 61 whichis composed of the P-channel type MOS transistor Qp64 and the N-channeltype MOS transistor Qn 62 is about 1/2 of the power-supply voltage VDD.Therefore, when the power-supply voltage VDD is about 4V, the electricpotential of the node N 64 which is connected with the input terminal ofthe first NOT circuit 61 becomes about 2V, so that the logical voltageof the node N 64, or the voltage detection signal VDT goes from "H" to"L", and the logical voltage of the output voltage signal VOUT 60 whichis the output of the second NOT circuit 62 goes from "L" to "H".

The current drain of the voltage detection circuit will explained asfollows. As shown in FIG. 24, when the power-supply voltage VDD is about4V, the node N 63 which is the input terminal of the first NOT circuit61 consisting of the P-channel type MOS transistor Qp 64 and theN-channel type MOS transistor Qn 62 has an intermediate electricpotential between the power-supply voltage VDD and the ground voltageVSS. Consequently, both the P-channel type MOS transistor Qp 64 and theN-channel type MOS transistor Qn 62 are in the on state, that is, thefirst NOT circuit 61 temporarily falls into the short-circuit state. Thecurrent drain In 60 which runs through the N-channel type MOS transistorQn 62 has a peak of 0.6 μA or so. Even when the power-supply voltage VDDis not about 4V, the current drain In 60 is 0.1 μA or higher as shown inFIG. 25.

However, in the conventional voltage detection circuit, when theelectric potential of the node N 63 which is the input of the first NOTcircuit 61 has an intermediate electric potential between thepower-supply voltage VDD and the ground voltage VSS, both the P-channeltype MOS transistor Qp 64 and the N-channel type MOS transistor Qn 62become the on state, that is, fall into temporary short-circuit state,which leads to an increase in the current drain. The current drain forthe entire voltage detection circuit is large in other states, too.

In view of these problems, the object of the present invention is toprovide a voltage detection circuit which reduces the peak of thecurrent drain in the temporary short-circuit state and decreases thecurrent drain as the entire circuit.

On the other hand, when a predetermined voltage is detected by thevoltage detection circuit, a power-on/off reset circuit for immediatelysuspending the operations of the devices such as a logic circuit or amemory circuit might destroy memory data in the memory circuit when theoperation is immediately suspended. Although there is no problem in thelogic circuit, the memory circuit needs data re-writing (restore orrefresh) after a readout. For this reason, it is difficult to properlyterminate a sequence in operation.

In view of these problems, another object of the present invention is toprovide a power-on/off reset circuit which properly terminates asequence in operation.

DISCLOSURE OF THE INVENTION

The present invention includes the voltage detection circuit,power-on/off reset circuit, and semiconductor device which areconstructed as follows.

The voltage detection circuit of the invention is characterized bycomprising a first MOS transistor whose gate and drain are connectedwith a first node, a second MOS transistor whose gate and drain areconnected with the first node and a third node, respectively, a firstresistive element which is connected between the first node and a secondnode, a second resistive element which is connected between the secondnode and a ground voltage terminal, a first NOT circuit whose inputterminal is connected with the second node, whose output terminal is afourth node, and which is connected between the third node and theground voltage terminal, and a second NOT circuit whose input terminalis connected with the fourth node and whose output terminal is a fifthnode.

The voltage detection circuit of the invention comprises a first MOStransistor whose gate and drain are connected with a first node, asecond MOS transistor whose gate and drain are connected with the firstnode and a third node, respectively, a first resistive element which isconnected between the first node and a second node, a second resistiveelement which is connected between the second node and a ground voltageterminal, a first NOT circuit whose input terminal is connected with thesecond node and whose output terminal is a fourth node, a second NOTcircuit whose input terminal is connected with the fourth node, whoseoutput terminal is a fifth node, and which is connected between a thirdnode and the ground voltage terminal, and a third MOS transistor whosegate is connected with the fifth node and which is connected betweeneither the ground voltage terminal or the power-supply voltage terminaland the fourth node.

In the invention, the first, second, and third MOS transistors of theinvention are P-channel type MOS transistors, and the source of thethird MOS transistor is connected with a power-supply voltage terminal.

The invention comprises a first voltage detection circuit which detectsa first voltage and outputs a first signal, and a second voltagedetection circuit which detects a second voltage lower than the firstvoltage and outputs a second signal, wherein the first voltage detectioncircuit comprises a first P-channel type MOS transistor whose gate anddrain are connected with a first node, a second P-channel type MOStransistor whose gate and drain are connected with the first node and athird node, respectively, a first resistive element which is connectedbetween the first node and a second node, a second resistive elementwhich is connected between the second node and a ground voltage, a NOTcircuit whose input terminal is the second node, whose output terminalis a fourth node, and which is connected between the third node and theground voltage terminal, and a third MOS transistor which is connectedbetween either the ground voltage terminal or a power-supply voltageterminal and the fourth node and whose gate is applied with the secondsignal of the second voltage detection circuit.

The invention is characterized in that in the invention, the secondsignal which is outputted from the second voltage detection circuit isoutputted only when the power supply is turned on.

The invention has a construction that in the invention the second signalwhich is outputted from the second voltage detection circuit isoutputted for a certain time period after the power supply is turned on.

The voltage detection circuit of the invention comprises a firstP-channel type MOS transistor whose gate and drain are connected with afirst node, a second P-channel type MOS transistor whose gate and drainare connected with the first node and a third node, respectively, afirst resistive element which is connected between the first node and asecond node, a second resistive element which is connected between thesecond node and a ground voltage terminal, an N-channel type MOStransistor whose gate is connected with the second node, and a first NOTcircuit whose input is the third node and whose output is a fourth node.

The invention has a construction that in the invention the firstresistive element is an N-channel type MOS transistor.

The power-on/off reset circuit of the invention comprises a firstvoltage detection circuit which detects a first voltage and outputs afirst signal, and prevents a new operational sequence when apower-supply voltage is equal to or lower than the first voltage.

The power-on/off reset circuit of the invention comprises a firstvoltage detection circuit which detects a first voltage and outputs afirst signal, and a second voltage detection circuit which detects asecond voltage lower than the first voltage and outputs a second signal,prevents a new operational sequence when a power-supply voltage is equalto or lower than the first voltage, and immediately suspends anoperation when the power-supply voltage is equal to or lower than thesecond voltage.

The power-on/off reset circuit of the invention comprises a firstvoltage detection circuit which detects a first voltage and outputs afirst signal, and a second voltage detection circuit which detects asecond voltage lower than the first voltage and outputs a second signal,wherein a time for a power-supply voltage to drop from the first voltageto the second voltage is longer than a predetermined operationalsequence completion time.

The voltage detection circuit comprises a first voltage detectioncircuit which (a) detects a first voltage and outputs a first signal,(b) outputs the first signal only when the power supply is turned on,and (c) outputs the first signal for a certain time period after thepower supply is turned on, a second voltage detection circuit whichdetects a second voltage and outputs a second signal, a third voltagedetection circuit which detects a third voltage higher than the secondvoltage, a fourth voltage detection circuit which detects a fourthvoltage higher than the third voltage and outputs a fourth signal, asignal selection circuit which selects either the third signal or thefourth signal and outputs a fifth signal, a first control circuit whichgenerates an OR output of the first signal and the second signal, and asecond control circuit which generates an OR output of the first signaland the fifth signal.

The power-on/off reset circuit comprises a voltage detection circuitwhich detects a first voltage and a second voltage higher than the firstvoltage and outputs a first signal, wherein the first signal istransmitted at the second voltage when a power-supply voltage rises, andtransmitted at the first voltage when the power-supply voltage drops,and a new operational sequence is prevented when the power-supplyvoltage is equal to or lower than the voltage for the first signal to betransmitted.

The power-on/off reset circuit comprises a first voltage detectioncircuit which detects a first voltage and a second voltage higher thanthe first voltage and outputs a first signal, and a second voltagedetection circuit which detects a third voltage which is lower than thefirst voltage and outputs a second signal, wherein the first signal istransmitted at the second voltage when a power-supply voltage rises, andtransmitted at the first voltage when the power-supply voltage drops, anew operational sequence is prevented when the power-supply voltage isequal to or lower than the voltage for the first signal to betransmitted, and an operation is immediately suspended when thepower-supply voltage is equal to or lower than the third voltage.

The power-on/off reset circuit comprises a first voltage detectioncircuit which detects a first voltage and a second voltage higher thanthe first voltage, and outputs a first signal, and a second voltagedetection circuit which detects a third voltage which is lower than thefirst voltage and outputs a second signal, wherein the first signal istransmitted at the second voltage when a power-supply voltage rises, andtransmitted at the first voltage when the power-supply voltage drops,and a time for a power-supply voltage to drop from the first voltage tothe third voltage is longer than a predetermined operational sequencecompletion time.

The semiconductor of the invention comprises the power-on/off resetcircuit and a non-volatile memory, and the semiconductor does notoperate the non-volatile memory when the power-supply voltage is equalto or lower than the first voltage.

The semiconductor of the invention comprises the power-on/off resetcircuit and a non-volatile memory, and the semiconductor does notoperate the non-volatile memory when the power-supply voltage is equalto or lower than the second voltage.

The semiconductor of the invention comprises the power-on/off resetcircuit and a non-volatile memory, and the semiconductor does notoperate the non-volatile memory when the power-supply voltage is equalto or lower than the voltage for the first signal to be transmitted orequal to or lower than the third voltage.

The semiconductor of the invention comprises the power-on/off resetcircuit and a non-volatile memory, and the semiconductor does notoperate the non-volatile memory when the power-supply voltage is equalto or lower than the voltage for the first signal to be transmitted orequal to or lower than the third voltage.

The inventions are voltage detection circuits which reduce the peak ofthe current drain and obtain a stable voltage detection signal. There isanother effect that the stable voltage detection signal can be obtainedeven at a low voltage of turning on the power-supply.

The inventions are power-on/off reset circuits which have an effect ofnot starting a new operational sequence mistakenly when the power supplyis turned on, and properly terminating a sequence in operation when thepower supply is turned off.

The inventions have an effect of obtaining an operation stable againstthe fluctuation of the power-supply voltage by applying voltagehysteresis to the power-on/off reset voltage.

The inventions have an effect of obtaining an operation stable againstthe fluctuation of the power-supply voltage by applying voltagehysteresis to the power-on/off reset voltage, thereby preventing thewrong operation of the non-volatile memory which is under the control ofthis signal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows the construction of the voltage detection circuit of thefirst embodiment of the present invention.

FIG. 2 shows the relationship between the power-supply voltage and theoutput voltage signal of the first embodiment of the present invention.

FIG. 3 shows the relationship between the power-supply voltage and thecurrent drain of the first embodiment of the present invention.

FIG. 4 shows the construction of the voltage detection circuit of thesecond embodiment of the present invention.

FIG. 5 shows the construction of the voltage detection circuit of thethird embodiment of the present invention.

FIG. 6 shows the waveform of the output signal when the power supply isturned on of the third embodiment of the present invention.

FIG. 7 shows the construction of the voltage detection circuit of thefourth embodiment of the present invention.

FIG. 8 shows the relationship between the power-supply voltage and theoutput voltage signal of the fourth embodiment of the present invention.

FIG. 9 shows the construction of the power-on/off reset circuit of thefifth embodiment of the present invention.

FIG. 10 shows the construction of the power-on/off reset circuit of thefifth embodiment of the present invention.

FIG. 11 shows the construction of the power-on/off reset circuit of thefifth embodiment of the present invention.

FIG. 12 shows the operational timing chart of the power-on/off resetcircuit of the fifth embodiment of the present invention.

FIG. 13 shows the construction of the power-on/off reset circuit of thesixth embodiment of the present invention.

FIG. 14 shows the operational timing chart of the sixth embodiment ofthe present invention.

FIG. 15 shows the operational timing chart of the sixth embodiment ofthe present invention.

FIG. 16 shows the construction of the power-on/off reset circuit of theseventh embodiment of the present invention.

FIG. 17 shows the construction of the power-on/off reset circuit of theeighth embodiment of the present invention.

FIG. 18 show the operational timing chart of the power-on/off resetcircuit of the eighth embodiment of the present invention.

FIG. 19 show the operational timing chart of the power-on/off resetcircuit of the ninth embodiment of the present invention.

FIG. 20 show the operational timing chart of the power-on/off resetcircuit of the ninth embodiment of the present invention.

FIG. 21 shows the circuit construction of the strong dielectric memoryunit of a semiconductor device provided with a non-volatile strongdielectric memory which is controlled by the power-on/off reset circuitof the tenth embodiment of the present invention.

FIG. 22 shows the operational timing chart of the strong dielectricmemory unit of the tenth embodiment of the present invention.

FIG. 23 shows the construction of a conventional voltage detectioncircuit.

FIG. 24 shows the relationship between the power-supply voltage and theoutput voltage signal of the conventional voltage detection circuit.

FIG. 25 shows the relationship between the power-supply voltage and thecurrent drain of the conventional voltage detection circuit.

    ______________________________________    (Description of reference numbers)    ______________________________________    Qp 11-Qp 64      P-channel type MOS transistors    Qn 11-Qn 62      N-channel type MOS transistors    VDD              power-supply voltage    VSS              ground voltage    11-31            NOT circuits    N 11-N 64        nodes    VDT 10-VDT 60    voltage detection signals    VOUT 10-VOUT 60  output voltage signals    In 10-In 60      current drain    BL, /BL          bit lines and their signals    WO 0-WL 255      word lines and their signals    CO 0-CP 255      cell plate electrodes and their    signals          bit line pre-charge control    BP    signal           sense amplifier control signal    SAE    ______________________________________

PREFERRED EMBODIMENTS OF THE INVENTION

The embodiments of the present invention will be explained hereinafter.

(Embodiment 1)

FIG. 1 shows the construction of the voltage detection circuit of thefirst embodiment of the present invention. FIG. 2 shows the relationshipbetween the power-supply voltage and the output voltage signal, and FIG.3 shows the relationship between the power-supply voltage and thecurrent drain.

The construction of the present embodiment will be explainedhereinafter. In FIG. 1, Qp 11-Qp 16 are P-channel type MOS transistors,Qn 11 and Qn 12 are N-channel type MOS transistors, and 11 and 12 areNOT circuits.

The source of the P-channel type MOS transistor Qp 11 is connected withthe power-supply voltage VDD, and its gate and drain are connected withthe node N 11. The source of the P-channel type MOS transistor Qp 12 isconnected with the power-supply voltage VDD, and its gate and drain areconnected with the node N 11 and the node N 13, respectively. TheP-channel type MOS transistors Qp 14 and Qp 15 are connected with eachother in series between the nodes N 11 and N 12. The N-channel type MOStransistor Qn 11 is connected between the node N 12 and the groundvoltage VSS. The serially-connected P-channel type MOS transistors Qp 14and Qp 15 and the N-channel type MOS transistor Qn 11 serve as resistiveelements. A NOT circuit 11 whose input terminal is the node N 12 andwhose output terminal is the node N 15 is connected between the node N13 and the ground voltage VSS. The NOT circuit 11 is made by seriallyconnecting the P-channel type MOS transistor Qp 13 and the N-channeltype MOS transistor Qn 12. The input terminal of the NOT circuit 12 isconnected with the node N 15 and the output terminal of the NOT circuit12 outputs a signal VOUT 10. A P-channel type MOS transistor Qp 16 whosegate is supplied with the signal VOUT 10 is connected between the node N15 and the power-supply voltage VDD.

As shown in FIG. 2, the present embodiment is so designed that when thepower-supply voltage VDD is about 3.5V or below, the logical voltage ofthe output of the signal VOUT 10 becomes "L", and when the power-supplyvoltage is about 3.5V or above, the logical voltage becomes "H".

With regard to the current drain of the present embodiment, as shown inFIG. 3, when the power-supply voltage VDD is about 3.5V, the electricpotential of the second node N 12 becomes intermediate between theground voltage VSS and the third node N 13. Consequently, both theP-channel type MOS transistor Qp 13 and the N-channel type MOStransistor Qn 12 are in the on state, that is, the first NOT circuit 11falls into a temporary short-circuit state, in which the current valuebecomes the highest. However, the increase in the current value isreduced by the P-channel type MOS transistor Qp 12, so that the currentdrain In 10 which runs through the transistor Qn 12 has its peak at 0.05μA. Even when the power-supply voltage is not about 3.5V, the currentdrain In 10 does not exceeds 0.1 μA.

Since the current value of the P-channel type MOS transistor Qp 12becomes about the same as the current value of the P-channel type MOStransistor Qp 11, the current which goes to the P-channel type MOStransistors Qp 11 and Qp 12 can be reduced by increasing the resistancevalue.

The current drain Ip 10 of the P-channel type MOS transistor Qp 12 canbe further reduced by making the driving ability of the P-channel typeMOS transistor Qp 12 equal to or lower than the driving ability of theP-channel type MOS transistor Qp 11.

Thus, in the present invention, the current drain can be reduced at 0.1μA or below within the operational power-supply voltage.

Furthermore, the P-channel type MOS transistor Qp 16 makes the node N 15be in the latch state, thereby stabilizing the signal VOUT 10.

(Embodiment 2)

FIG. 4 shows the construction of the voltage detection circuit of thesecond embodiment of the present invention.

In the present embodiment, a voltage detection circuit 41 which candetect a lower voltage than in the first embodiment is added, the outputsignal VDT 20 whose logical voltage is "H" is supplied to the gate ofthe P-channel type MOS transistor Qp 17 at the low voltage of thevoltage detection circuit 41, and this transistor Qp 17 is connectedbetween the node N 15 and the power-supply voltage VDD. The presentembodiment can prevent the circuit of FIG. 1 from becoming unstable ataround 1.5V shown in FIG. 2.

As a result, this circuit can achieve a stable operation at a lowvoltage especially when the power supply is turned on, by means of asignal from a voltage detection circuit which detects a lower voltagethan the voltage of the circuit itself.

(Embodiment 3)

FIG. 5 shows the construction of the voltage detection circuit of thethird embodiment of the present invention, and FIG. 6 shows the waveformof the output signal when the power supply is turned on.

The present embodiment can be used in the voltage detection circuit 41of the second embodiment.

The sources of the P-channel type MOS transistors QP 21-Qp 24, the gatesof the transistors Qp 21 and Qp 24 are connected with the power-supplyvoltage VDD. The drains of the transistors Qp 21-Qp 22 and the gates ofthe transistors Qp 22-Qp23 are connected with the node N 21. The drainsof the transistors Qp 23-Qp24 are connected with the node N 23. Thesource of the P-channel type MOS transistor Qp 25 is connected with thenode N 21, and its gate and drain are connected with the node N 22. Aresistance R 21 is connected between the node N 22 and the groundvoltage VSS. The N-channel type MOS transistor Qn 21 whose gate is thenode N 23 is connected between the power-supply voltage VDD and the nodeN 23 via the resistance R 22. The capacity C 21 is connected between thenode N 23 and the ground voltage VSS. The P-channel type MOS transistorQp 26 whose gate is the ground voltage VSS and the P-channel type MOStransistor Qp 27 whose gate is the node N 26 are connected with eachother in parallel between the nodes N 23 and N 24. The NOT circuit 21whose input is the node N 24 and whose output is the node N 26 isconnected in serial with the NOT circuit 22 whose input is the node N 26and whose output is the signal VDT 20. The capacity C22 is connectedbetween the node N 24 and the ground voltage VSS. The gate and source ofthe N-channel type MOS transistor Qn 22 are connected with the node N 24and its drain is connected with the node N 25. The source of theP-channel type MOS transistor Qp 28 is connected with the node N 24 andits gate and drain are connected with the node N 25. The resister R 23is connected between the node N 25 and the power-supply voltage VDD.

In this circuit, the node N 23 which is connected with the capacity C 21is supplied with charges via the P-channel type MOS transistor Qp 23whose current is restricted. The node N 23 can be regarded as a voltagesource whose voltage rises slowly. The NOT circuit 21 receives thevoltage of the node N 24 which is determined by the charge supply fromthe node N 23 and outputs the voltage to the node N 26. The node N 22receives the voltage and outputs the voltage detection signal VDT 20.The switching voltage level of the NOT circuit 21 is set high. Since thevoltage of the node N 23 rises slowly, the voltage detection signal VDT20 increases t1 time after the power-supply voltage VDD is turned on asshown in FIG. 6. The time t1 is determined by the current abilitybetween the capacity C 21 and the P-channel type MOS transistor Qp 23and the current ability between the capacity C 22 and the P-channel typeMOS transistor Qp 26. This circuit is characterized in that the voltagedetection signal VDT 20 is outputted when the power-supply voltage isturned on, but not outputted when the power-supply voltage is turnedoff.

The use of the present embodiment as a voltage detection circuit or apower-on/off reset circuit for the voltage detection circuit 41 of thesecond embodiment makes it possible to realize a stable operation whenthe power supply is turned on.

(Embodiment 4)

FIG. 7 shows the construction of the voltage detection circuit of thefourth embodiment of the present invention, and FIG. 8 shows therelationship between the power-supply voltage and the output voltagesignal.

Firstly, the construction of the present embodiment will be explained asfollows. In FIG. 7, Qp 11 and Qp 12 are P-channel type MOS transistors,Qn 11-Qn 13 are N-channel type MOS transistors, and 31 represents a NOTcircuit.

The source of the P-channel type MOS transistor Qp 11 is connected withthe power-supply voltage VDD, and its gate and drain are connected withthe node N 11. The source of the P-channel type MOS transistor Qp 12 isconnected with the power-supply voltage VDD, and its gate and drain areconnected with the node N 11 and the node N 13, respectively. TheN-channel type MOS transistor Qn 12 is connected between the node N 11and the node N 12. The N-channel type NOS transistor Qn 11 is connectedbetween the node N 12 and the ground voltage VSS. The N-channel type MOStransistor Qn 13 whose gate is the node N 12 is connected between thenode N 13 and the ground voltage VSS. The input terminal of the NOTcircuit 31 is connected with the node N 13, and the output terminalthereof outputs the signal VOUT 30.

As shown in FIG. 8, the present embodiment so operates that the logicalvoltage of the operation signal VOUT 30 becomes "L" when thepower-supply voltage VDD is about less than 2.0V and becomes "H" whenthe power-supply voltage VDD is about 2.0V or above.

In the present embodiment, the power-supply voltage VDD is lowered bythe threshold value of the P-channel type MOS transistor Op 11, anddivided between N-channel type MOS transistors Qn 12 and Qn 11. Thedivided voltage is outputted to the node N 12. The voltage of the node N12 makes the N-channel type MOS transistor Qn 13 be turned on and off,thereby determining the signal VOUT 30. Thus, the detection signal witha low voltage can be obtained by dividing the power-supply voltagebetween N-channel type MOS transistors Qn 12 and Qn 11. Another voltagedetection signal can be obtained by changing the voltage division ratiobetween the N-channel type MOS transistors Qn 12 and Qn 11 or providingan additional node which offers a divided voltage different from thenode N 12 by connecting another N-channel type MOS transistor with thetransistors Qn 12 and Qn 11 in series. Furthermore, the circuit may beso constructed that the ability of the N-channel type MOS transistor Qn12 can be renewed by replacing its fuse or the like. The presentembodiment does not demand large power consumption, and is applicable tothe circuit 41 of the second embodiment.

(Embodiment 5)

FIGS. 9, 10, and 11 show the construction of the power-on/off resetcircuit of the fifth embodiment of the present invention. FIG. 12 showsthe timing chart of the operation. In the drawings, VDD, CLK, CE, andICE represent a power-supply voltage, a reference clock, a controlsignal, and an internal control signal, respectively.

The present embodiment is composed of a voltage detection circuit 43which outputs a voltage detection signal VDT 21, a reference clockgeneration circuit 47 which outputs a reference clock CLK, a controlsignal CE generation circuit 48 which outputs a control signal CE fromthe voltage detection signal VDT 21 and the control signal (sic.) CLK,and an internal control signal ICE generation circuit 49 which outputsan internal control signal ICE from the control signal CE. The presentembodiment prevents a new operational sequence when the voltage is equalto or lower than the voltage which is detected by the voltage detectionsignal VDT 21, and completes an on-going sequence.

When the power-supply voltage is equal to or higher than the voltagewhich is detected by the voltage detection signal VDT 21, the controlsignal CE has the reversed phase of the reference clock CLK. On theother hand, when the power-supply voltage is lower than the voltagewhich is detected by the voltage detection signal VDT 21, the controlsignal CE has a logical voltage of "H". FIG. 11 shows a circuit whichmakes an on-going sequence be completed, and generates a pulse signalwhich has a certain delay time from the trailing edge of the controlsignal CE.

When the power-supply voltage is equal to or higher than the voltagewhich is detected by the voltage detection signal VDT 21, the internalcontrol signal ICE has the same waveform as the external input controlsignal CE. When the power-supply voltage becomes lower than the voltagedetection signal VDT 21 at time t6, the logical voltage of the internalcontrol signal ICE is kept at "L" even if the logical voltage of theexternal input control signal CE becomes "H", and goes to "H" at time t6(sic.). Even when the logical voltage of the external input controlsignal CE becomes "L" at t8, the logical voltage of the internal controlsignal ICE is kept at "H".

In the power-on/off reset of this operation, an ongoing sequence can becompleted even if the power supply is decreased, and a new operationalsequence can be prevented. Consequently, the circuit can be used for astrong dielectric memory which is a non-volatile memory demandingre-writing of data.

(Embodiment 6)

FIG. 13 shows the construction of the power-on/off reset circuit of thesixth embodiment of the present invention, and FIGS. 14 and 15 show thetiming chart of the operation.

The present embodiment includes two voltage detection circuits 42 and 43which output voltage detection signals VDT 30 and VDT 31, respectively.The voltage detection signal VDT 30 detects a lower voltage than thevoltage detection signal VDT 31. A new operational sequence is preventedwhen the voltage is equal to or lower than the voltage which is detectedby the voltage detection signal VDT 31 (t10 in FIG. 15), and theoperation is immediately suspended when the voltage is equal to or lowerthan the voltage which is detected by the voltage detection signal VDT30 (t13 in FIG. 14). Furthermore, a certain time period is secured foran on-going sequence to be completed before the power-supply voltagedrops from the voltage detection signal VDT 31 to the voltage detectionsignal VDT 30.

In this circuit, the voltage detection signal VDT 30 of the voltagedetection circuit 42 controls a WL (word line signal)•CP (cell plateline signal)•SAE (sense amplifier enable signal) control circuit 44,while the voltage detection signal VDT 31 of the voltage detectioncircuit 43 controls ICE (internal control signal) control circuit 45.

In FIG. 14, VDD, CE, ICE, and WL represent a power-supply voltage, anexternal input control signal, an internal control signal, and a wordline signal, respectively. When the power-supply voltage VDD is equal toor higher than the voltage which is detected by the voltage detectionsignal VDT 31, the internal control signal ICE operates the same way asthe external input control signal CE. When the power-supply voltage VDDbecomes equal to the voltage detection signal VDT 31 at time t11, evenif the logical voltage of the external input control signal CE is at"L", when the power-supply voltage VDD becomes equal to or lower thanthe voltage detection signal VDT 30, the internal control signal ICEkeeps it logical voltage at "L" until time t13, and then goes to "H".When the power-supply voltage VDD becomes equal to or lower than thevoltage detection signal VDT 30, the word line signal WL immediatelysuspends the operation. Therefore, the logical voltage of the word linesignal WL is set at "L" without fail when the power supply is turned onand in other conditions, which prevents the wrong operation of thememory cell in a strong dielectric memory.

(Embodiment 7)

FIG. 16 shows the construction of the power-on/off reset circuit of theseventh embodiment of the present invention. The present embodiment iscomposed of the power-on reset circuit 41 of the third embodiment whichoutputs the voltage detection signal VDT 20, the voltage detectioncircuits 42 and 43 of the fourth embodiment which output the voltagedetection signals VDT 30 and VDT 31, respectively, the voltage detectioncircuit 40 of the first embodiment which outputs the voltage detectionsignal VDT 10, a 3V/5V version switch circuit 46, the WL (word linesignal)•CP (cell plate line signal)•SAE (sense amplifier enable signal)control circuit 44, and the ICE (internal control signal) controlcircuit 45. The control circuit 44 is controlled by, for example, an ORsignal of the voltage detection signals VDT 20 and VDT 30, and eitherthe voltage detection signal VDT 31 or VDT 10 is selected by the 3V/5Vversion switch circuit 46. For example, the voltage detection signal VDT31 is selected in the 3V version device, and the voltage detectionsignal VDT 10 is selected in the 5V version device. The control circuit45 is controlled by the OR signal of the selected signal and the voltagedetection signal VDT 20. The present embodiment is an application of theabove-described embodiments, and can use both the 3V version and 5Vversion devices, thereby completely protecting data when the powersupply is turned on or off in a non-volatile memory such as a strongdielectric memory.

(Embodiment 8)

In the eighth embodiment, the voltage detection signal VDT 21 of thefifth embodiment is provided with a voltage hysteresis. FIG. 17 showsthe construction of the circuit of the eighth embodiment of the presentinvention and FIG. 18 shows the operational timing chart of thepower-on/off reset circuit. In these drawings, VDD, CE, and ICErepresent a power-supply voltage, an external input control signal, andan internal control signal, respectively.

The present embodiment includes a voltage detection circuit whichdetects the detection voltages VDT 30 and VDT 31 and generates thevoltage detection signal DT 21 which is detected by the voltagedetection signals DT 30 and DT 31 and has a power-supply voltagehysteresis (the circuit 54 shown in FIG. 17). When the logical voltageof the voltage detection signal DT 21 is at "H", a new operationalsequence is prevented.

The internal control signal ICE has a fixed time period which starts atthe point where the logical voltage of the OR signal of the voltagedetection signal DT 21 and the external input control signal CE goes to"L". In short, the internal control signal ICE keeps its logical voltageat "L" for a fixed time period even if the logical voltage of theexternal input control signal CE goes to "H".

In the power-on/off reset of this operation, an on-going sequence can becompleted even if the power supply is decreased, and a new operationalsequence can be prevented. Consequently, it is effectively used for astrong dielectric memory which is a non-volatile memory demandingre-writing of data. Furthermore, since the voltage detection signal DT21 with a power-supply voltage hysteresis is outputted through the twovoltage detection signals DT 30 and DT 31, the voltage detection signalto be outputted is stable against the fluctuation of the power-supplyvoltage. As a result, data in the non-volatile memory can be preventedfrom being destroyed at a low voltage.

(Embodiment 9)

FIG. 19 shows the construction of the power-on/off reset circuit of theninth embodiment of the present invention, and FIG. 20 shows the timingchart of the operation. The present embodiment has a voltage detectionsignal DT 32 which detects a further lower power-supply voltage inaddition to the voltage detection signals DT 30 and DT 31 of the sixthembodiment, and which controls the power-supply voltage hysteresis withthe voltage detection signals DT 30 and DT 31. The voltage detectionsignal DT 32 is outputted from the voltage detection signal selectioncircuit 56 which generates the OR of the power-on reset circuit 41 andthe voltage detection circuit 42, and controlled by both the wait resetsignal of the power-on reset circuit 41 when the power supply is turnedon and the detection signal of the voltage detection circuit 42 for lowvoltage.

The internal control signal ICE is controlled by the VDT 31 when thepower-supply voltage increases, and controlled by the VDT 30 when thepower-supply voltage decreases. These voltage detection signals VDT 30and VDT 31 prevent a new operational sequence, and immediately suspendthe operation when the voltage is equal to or lower than the voltagewhich is detected by the voltage detection signal VDT 32. Furthermore, acertain time period is secured for an on-going sequence to be completedbefore the power-supply voltage drops from the voltage detection signalVDT 30 to the voltage detection signal VDT 32. When the power-supplyvoltage is equal to or lower than the VDT 32, the word line signal WLimmediately suspends the operation. Consequently, for example, when thepower supply is turned on, the logical voltage of the word line signalWL is set at "L" without fail and the wrong operation of a memory cellin a strong dielectric memory can be prevented.

(Embodiment 10)

The tenth embodiment is an application of a strong dielectric memoryunit in an RF-ID tag semiconductor device or the like which is providedwith the voltage detection circuit, power-on /off reset circuit, andnon-volatile strong dielectric memory of the above-explainedembodiments.

In the present embodiment, a one-bit memory cell is composed of twostrong dielectric capacitors and two transistors, and these capacitorsstore complementary data. FIG. 21 shows the construction of the entirecircuit, and FIG. 22 shows the timing chart of the operation. In thesedrawings, WL 0-WL 255 represent word lines, BL and /BL represent bitlines, CP 0-CP 255 represent cell plate electrodes, BP represents a bitline pre-charge control signal, SAE represents a sense amplifier controlsignal, VSS represents a ground voltage, SA represents a senseamplifier, C 0-C 255 and C 0B-C 255B represent memory cell capacitors,and Qn 0-Qn 255, Qn 0B-Qn 255B, and Qn BP0-Qn BP2 represent N-channeltype MOS transistors. The construction of the circuit shown in FIG. 21will be explained briefly as follows. The sense amplifier SA isconnected with the bit lines BL and /BL. The sense amplifier SA iscontrolled by the sense amplifier control signal SAE. The firstelectrode of the memory cell capacitor C 0 is connected with the bitline BL via the memory cell transistor Qn 0 whose gate electrode isconnected with the word line WL 0, and the second electrode is connectedwith the cell plate electrode CP 0. The first electrode of the memorycell capacitor C 0B which is the pair to the memory cell capacitor C 0is connected with the bit line /BL via the memory cell transistor Qn 0Bwhose gate electrode is connected with the word line WL 0, and thesecond electrode is connected with the cell plate electrode CP 0. Theconnections of the other memory cell capacitors C 1-C 255 and C 1B-C255B are the same as the memory cell capacitors C 0 and C 0B.Furthermore, the bit lines BL and /BL are connected with each other viathe N-channel type MOS transistor Qn BP2. The bit line BL and the groundvoltage VSS are connected with each other via the N-channel type MOStransistor Qn BP0, and the bit line /BL and the ground voltage VSS areconnected with each other via the N-channel type MOS transistor Qn BP1.The gate electrodes of the N-channel type MOS transistors Qn BP0-Qn BP2are connected with the bit line pre-charge control signal BP. Theoperation of the strong dielectric memory device circuit will beexplained as follows with reference to the operational timing chartshown in FIG. 22. Firstly, in order to read data from the memory cell,the logical voltage of the bit lines BL and /BL is set at "L" by settingthe logical voltage of the bit line pre-charge control signal BP at "H".Furthermore, the word line WL 0-WL 255 and the cell plate electrode CPare made the ground voltage VSS whose logical voltage is "L". Next, thelogical voltage of the bit line pre-charge control signal BP is set at"L", thereby putting the bit lines BL and /BL in the floating state.Then, the logical voltage of the word line WL 0 and the cell plateelectrode CP is set at "H", thereby reading out data from the memorycell capacitors C 0 and C 0B to the bit lines BL and /BL. Then, thelogical voltage of the cell plate electrode CP is set at "L", so thatthe data of the memory cell capacitors C 0 and C 0B are re-written.Then, the logical voltage of the word line WL 0 is set at "L" so that novoltage is applied on the memory cell capacitors C 0 and C0 B. Then, thelogical voltage of the sense amplifier control signal SAE is set at "L",to suspend the operation of the sense amplifier SA. Then, the logicalvoltage of the bit line pre-charge control signal BP is set at "H",thereby returning the logical voltage of the bit lines BL and /BL to theinitial state of "L".

Thus, if the voltage detection circuit and the power-on/off resetcircuit of the present invention are used for the control of the strongdielectric memory, the destruction of data in the strong dielectricmemory at a low voltage can be prevented, and as a result, a highlyreliable device can be achieved.

Possibility of Industrial Use

The voltage detection circuit of the present invention can reduce thepeak of the current drain and stabilize the voltage detection signal.

In addition, in the power-on/off reset of the present invention, no newoperational sequence is mistakenly started when the power supply isturned on, and an on-going sequence can be properly terminated when thepower supply is turned off.

Furthermore, the semiconductor of the present invention can prevent thewrong operation of a non-volatile memory.

What is claimed is:
 1. A voltage detection circuit comprising a firstMOS transistor whose gate and drain are connected with a first node andsource connected with a power supply voltage, a second MOS transistorwhose gate and drain are connected with the first node and a third node,respectively, and source connected with the power supply voltage, afirst resistive element which is connected between the first node and asecond node, a second resistive element which is connected between thesecond node and a ground voltage terminal, a first NOT circuit whoseinput terminal is connected with the second node, whose output terminalis a fourth node, and the first NOT circuit is connected between thethird node and the ground voltage terminal, and a second NOT circuitwhose input terminal is connected with the fourth node and whose outputterminal is a fifth node.
 2. A voltage detection circuit comprising afirst MOS transistor whose gate and drain are connected with a firstnode and source connected with a power supply voltage, a second MOStransistor whose gate and drain are connected with the first node and athird node, respectively, and source connected with the power supplyvoltage, a first resistive element which is connected between the firstnode and a second node, a second resistive element which is connectedbetween the second node and a ground voltage terminal, a first NOTcircuit whose input terminal is connected with the second node and whoseoutput terminal is a fourth node, a second NOT circuit whose inputterminal is connected with the fourth node, whose output terminal is afifth node, and the first NOT circuit is connected between a third nodeand the ground voltage terminal, and a third MOS transistor whose gateis connected with the fifth node and the third MOS transistor isconnected between either the ground voltage terminal or the power-supplyvoltage terminal and the fourth node.
 3. The voltage detection circuitof claim 2, wherein the first, second, and third MOS transistors areP-channel type MOS transistors, and the source of the third MOStransistor is connected with a power-supply voltage terminal.
 4. Avoltage detection circuit comprising a first voltage detection circuitwhich detects a first voltage and outputs a first signal and a secondvoltage detection circuit which detects a second voltage lower than thefirst voltage and outputs a second signal, wherein the first voltagedetection circuit comprises a first P-channel type MOS transistor whosegate and drain are connected with a first node and source connected witha power supply voltage, a second P-channel type MOS transistor whosegate and drain are connected with the first node and a third node,respectively, and source connected with the power supply voltage, afirst resistive element which is connected between the first node and asecond node, a second resistive element which is connected between thesecond node and a ground voltage, a NOT circuit whose input terminal isthe second node, whose output terminal is a fourth node, and the NOTcircuit is connected between the third node and the ground voltageterminal, and a third MOS transistor which is connected between eitherthe ground voltage terminal or a power-supply voltage terminal and thefourth node and whose gate is applied with the second signal of thesecond voltage detection circuit.
 5. The voltage detection circuit ofclaim 4 characterized in that the second signal which is outputted fromthe second voltage detection circuit is outputted only when the powersupply is turned on.
 6. The voltage detection circuit of claim 4,wherein the second signal which is outputted from the second voltagedetection circuit is outputted for a certain time period after the powersupply is turned on.
 7. A voltage detection circuit characterized bycomprising a first P-channel type MOS transistor whose gate and drainare connected with a first node and source connected with a power supplyvoltage, a second P-channel type MOS transistor whose gate and drain areconnected with the first node and a third node, respectively, and sourceconnected with the power supply voltage, a first resistive element whichis connected between the first node and a second node, a secondresistive element which is connected between the second node and aground voltage terminal, an N-channel type MOS transistor whose gate isconnected with the second node, whose drain is connected with the thirdnode and whose source is connected with the ground voltage terminal, anda first NOT circuit whose input is the third node and whose output is afourth node.
 8. The voltage detection circuit of claim 7 characterizedin that the first resistive element is an N-channel type MOS transistor.9. A voltage detection circuit for detecting when a power supply voltage(1) exceeds a predetermined magnitude for producing a selected highvoltage level "H" at a voltage detection circuit output and (2) is lessthan the predetermined magnitude for producing a selected low voltagelevel "L" at the voltage detection circuit output comprising:a first MOStransistor having a gate and a drain both connected to a first node anda source connected to a power supply voltage; a second MOS transistorhaving a gate and a drain connected to the first node and a third node;respectively, and a source connected to the power supply voltage; afirst resistive element connected between the first node and a secondnode; a second resistive element connected between the second node and aground terminal; a first NOT circuit having an input terminal connectedto the second node, and an output terminal forming a fourth node, thefirst NOT circuit being coupled between the third node and the groundterminal; and a second NOT circuit having an input terminal connected tothe fourth node and an output terminal being the voltage detectioncircuit output, wherein the voltage detection circuit output becomes thehigh voltage level "H" when the power supply voltage exceeds thepredetermined magnitude, and becomes the low voltage level "L" when thepower supply voltage is below the predetermined magnitude.
 10. Thevoltage detection circuit of claim 9, in which a third MOS transistorhas a gate connected to the voltage detection circuit output, a drainconnected to the fourth node and a source connected to the power supplyvoltage, wherein the third MOS transistor latches the voltage of thevoltage detection circuit output.